Memory device including multiple gate-induced drain leakage current generator circuits

ABSTRACT

Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.15/416,870, filed Jan. 26, 2017, which is incorporated herein byreference in its entirety.

BACKGROUND

Memory devices are widely used in computers and many electronic items tostore information. A memory device usually has numerous memory cells.The memory device performs a write operation to store information in thememory cells, a read operation to retrieve the stored information, andan erase operation to clear information (e.g., obsolete information)from some or all of the memory cells. The reliability of theseoperations highly depends on the structure of the memory device and thetechniques used to operate it. Some conventional memory devices havestructures and operations that are reliable for some applications butunsuitable for other applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice, according to some embodiments described herein.

FIG. 2A shows a block diagram of a portion of a memory device includinga memory array having top and bottom gate-induced drain leakage (GIDL)current generator circuits, according to some embodiments describedherein.

FIG. 2B shows a schematic diagram of the memory device of FIG. 2A,according to some embodiments described herein.

FIG. 2C shows a schematic diagram of a portion of the memory device ofFIG. 2B, according to some embodiments described herein.

FIG. 2D shows example waveforms of some of the signals of the memorydevice of FIG. 2A through FIG. 2C during example erase, write, and readoperations, according to some embodiments described herein.

FIG. 3 shows a side view of a structure of a portion of the memorydevice of FIG. 2A through FIG. 2C, according to some embodimentsdescribed herein.

FIG. 4 is a graph showing an example relationship between the locationof an interface in a pillar of the memory device of FIG. 3 and an eraseGIDL current generated during an erase operation of the memory device,according to some embodiments described herein.

FIG. 5A shows a block diagram of a portion of a memory device, which canbe a variation of the memory device of FIG. 2A, according to someembodiments described herein.

FIG. 5B shows a schematic diagram of the memory device of FIG. 5A,according to some embodiments described herein.

FIG. 5C shows a schematic diagram of a portion of the memory device ofFIG. 5B, according to some embodiments described herein.

FIG. 5D shows example waveforms of some of the signals of the memorydevice of FIG. 5A through FIG. 5C during example erase, write, and readoperations, according to some embodiments described herein.

FIG. 6 shows a side view of a structure of a portion of the memorydevice of FIG. 5A through FIG. 5C, according to some embodimentsdescribed herein.

FIG. 7 is a graph showing an example relationship between the locationof an interface in a pillar of the memory device of FIG. 6 and eraseGIDL current generated during an erase operation and of the memorydevice, according to some embodiments described herein.

FIG. 8A shows a block diagram of a portion of a memory device, which canbe a variation of the memory device of FIG. 2A and the memory device ofFIG. 5A, according to some embodiments described herein.

FIG. 8B shows a schematic diagram of the memory device of FIG. 8A,according to some embodiments described herein.

FIG. 8C shows a schematic diagram of a portion of the memory device ofFIG. 8B, according to some embodiments described herein.

FIG. 8D shows example waveforms of some of the signals of the memorydevice of FIG. 8A through FIG. 8C during example erase, write, and readoperations, according to some embodiments described herein.

FIG. 9 shows a side view of a structure of a portion of the memorydevice of FIG. 8A through FIG. 8C, according to some embodimentsdescribed herein.

FIG. 10, FIG. 11, and FIG. 12 show sequential stages in exampleprocesses of forming a memory device, according some embodimentsdescribed herein.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of an apparatus in the form of a memorydevice 100, according to some embodiments described herein. Memorydevice 100 can include a memory array (or multiple memory arrays) 101containing memory cells 102 arranged in blocks (memory cell blocks),such as blocks 103 ₀ and 103 ₁. In the physical structure of memorydevice 100, memory cells 102 can be arranged vertically (e.g., stackedover each other) over a substrate (e.g., a semiconductor substrate) ofmemory device 100. FIG. 1 shows memory device 100 having two blocks 103₀ and 103 ₁ as an example. Memory device 100 can have more than twoblocks (e.g., up to thousands or more blocks).

As shown in FIG. 1, memory device 100 can include access lines (whichcan include word lines) 150 and data lines (which can include bit lines)170. Access lines 150 can carry signals (e.g., word line signals) WL0through WLm. Data lines 170 can carry signals (e.g., bit line signals)BL0 through BLn. Memory device 100 can use access lines 150 toselectively access memory cells 102 of blocks 103 ₀ and 103 ₁ and datalines 170 to selectively exchange information (e.g., data) with memorycells 102 of blocks 103 ₀ and 103 ₁.

Memory device 100 can include an address register 107 to receive addressinformation (e.g., address signals) ADDR on lines (e.g., address lines)103. Memory device 100 can include row access circuitry 108 and columnaccess circuitry 109 that can decode address information from addressregister 107. Based on decoded address information, memory device 100can determine which memory cells 102 of which of blocks 103 ₀ and 103 ₁are to be accessed during a memory operation. Memory device 100 canperform a read operation to read (e.g., sense) information (e.g.,previously stored information) in memory cells 102 of blocks 103 ₀ and103 ₁, or a write (e.g., programming) operation to store (e.g., program)information in memory cells 102 of blocks 103 ₀ and 103 ₁. Memory device100 can use data lines 170 associated with signals BL0 through BLn toprovide information to be stored in memory cells 102 or obtaininformation read (e.g., sensed) from memory cells 102. Memory device 100can also perform an erase operation to erase information from some orall of memory cells 102 of blocks 103 ₀ and 103 ₁.

Memory device 100 can include a control unit 118 that can be configuredto control memory operations of memory device 100 based on controlsignals on lines 104. Examples of the control signals on lines 104include one or more clock signals and other signals (e.g., a chip enablesignal CE#, a write enable signal WE#) to indicate which operation(e.g., read, write, or erase operation) memory device 100 can perform.

Memory device 100 can include sense and buffer circuitry 120 that caninclude components such as sense amplifiers and page buffer circuits(e.g., data latches). Sense and buffer circuitry 120 can respond tosignals BL_SEL0 through BL_SELn from column access circuitry 109. Senseand buffer circuitry 120 can be configured to determine (e.g., bysensing) the value of information read from memory cells 102 (e.g.,during a read operation) of blocks 103 ₀ and 103 ₁ and provide the valueof the information to lines (e.g., global data lines) 175. Sense andbuffer circuitry 120 can also can be configured to use signals on lines175 to determine the value of information to be stored (e.g.,programmed) in memory cells 102 of blocks 103 ₀ and 103 ₁ (e.g., duringa write operation) based on the values (e.g., voltage values) of signalson lines 175 (e.g., during a write operation).

Memory device 100 can include input/output (I/O) circuitry 117 toexchange information between memory cells 102 of blocks 103 ₀ and 103 ₁and lines (e.g., I/O lines) 105. Signals DQ0 through DQN on lines 105can represent information read from or stored in memory cells 102 ofblocks 103 ₀ and 103 ₁. Lines 105 can include nodes within memory device100 or pins (or solder balls) on a package where memory device 100 canreside. Other devices external to memory device 100 (e.g., a memorycontroller or a processor) can communicate with memory device 100through lines 103, 104, and 105.

Memory device 100 can receive a supply voltage, including supplyvoltages Vcc and Vss. Supply voltage Vss can operate at a groundpotential (e.g., having a value of approximately zero volts). Supplyvoltage Vcc can include an external voltage supplied to memory device100 from an external power source such as a battery or alternatingcurrent to direct current (AC-DC) converter circuitry.

Each of memory cells 102 can be programmed to store informationrepresenting a value of at most one bit (e.g., a single bit) or a valueof multiple bits such as two, three, four, or another number of bits.For example, each of memory cells 102 can be programmed to storeinformation representing a binary value “0” or “1” of a single bit. Thesingle bit per cell is sometimes called a single-level cell. In anotherexample, each of memory cells 102 can be programmed to store informationrepresenting a value for multiple bits, such as one of four possiblevalues “00”, “01”, “10”, and “11” of two bits, one of eight possiblevalues “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” ofthree bits, or one of other values of another number of multiple bits. Acell that has the ability to store multiple bits is sometimes called amulti-level cell (or multi-state cell).

Memory device 100 can include a non-volatile memory device, and memorycells 102 can include non-volatile memory cells, such that memory cells102 can retain information stored thereon when power (e.g., voltage Vcc,Vss, or both) is disconnected from memory device 100. For example,memory device 100 can be a flash memory device, such as a NAND flash(e.g., 3-dimensional (3-D) NAND) or a NOR flash memory device, oranother kind of memory device, such as a variable resistance memorydevice (e.g., a phase change memory device or a resistive RAM (RandomAccess Memory) device).

One of ordinary skill in the art may recognize that memory device 100may include other components, several of which are not shown in FIG. 1so as not to obscure the example embodiments described herein. At leasta portion of memory device 100 can include structures and performoperations similar to or identical to the structures and operations ofany of the memory devices described below with reference to FIG. 2through FIG. 12.

FIG. 2A shows a block diagram of a portion of a memory device 200including a memory array 201 having circuits 285_1, 285_2, 285_3, 285_4,287_1, 287_2, 287_3, 287_4, memory cell strings 231 through 240, 291,and 292, select circuits 241 through 252 and 241′ through 252′,according to some embodiments described herein. Memory device 200 cancorrespond to memory device 100 of FIG. 1. For example, memory array 201can form part of memory array 101 of FIG. 1.

As described in more detailed with reference to FIG. 2B, FIG. 2C, andFIG. 2D, circuits 285_1, 285_2, 285_3, and 285_4 and circuits 287_1,287_2, 287_3, 287_4 can be used to generate GIDL current to help improvean erase operation of memory device 200. Thus, circuits 285_1, 285_2,285_3, and 285_4 can be called current generator circuits (e.g., topGILD current generator circuits) and circuits 287_1, 287_2, 287_3, 287_4can also be called current generator circuits (e.g., bottom GIDL currentgenerator circuits). In FIG. 2A, “C.G. Circuit” stands for “currentgenerator circuit”.

As shown in FIG. 2A, memory device 200 can include blocks (blocks ofmemory cells) 203 ₀ and 203 ₁. Two blocks are shown as an example.Memory device 200 can include many blocks (e.g., up to thousands or moreblocks). Each of blocks 203 ₀ and 203 ₁ has its own memory cell stringsand associated select circuits and GIDL current generator circuits. Forexample, block 203 ₀ has memory cell strings 231 through 236, selectcircuits 241 through 246 and 241′ through 246′, circuits 285_1 and285_2, and circuits 287_1 and 287_2. Block 203 ₁ has memory cell strings237 through 240, 291, and 292, select circuits 247 through 252 and 247′through 252′, circuits 285_3 and 285_4, and circuits 287_3 and 287_4.

Each of memory cell strings 231 through 240, 291, and 292 has memorycells (shown in FIG. 2B) arranged in a string (e.g., coupled in seriesamong each other) to store information. During an operation (e.g., writeor read) of memory device 200, memory cell strings 231 through 240, 291,and 292 can be individually selected to access the memory cells in theselected memory cell string in order to store information in or retrieveinformation from the selected memory cell strings. Thus, in a writeoperation, the selected memory cell strings are memory cell strings(among memory cell strings 231 through 240, 291, and 292) selected tostore information in selected memory cells of the selected memory cellstrings. In a read operation, the selected memory cell strings arememory cell strings (among memory cell strings 231 through 240, 291, and292) selected to read information from selected memory cells of theselected memory cell strings. During an erase operation, some or all ofthe memory cell strings in a particular block can be selected (e.g.,concurrently selected) to erase information from them.

Each of the memory cell strings 231 through 240, 291, and 292, can beassociated with (e.g., coupled to) two select circuits and two currentgenerator circuits. For example, memory cell string 231 is associatedwith select circuit (e.g., top select circuit) 241, select circuit(e.g., bottom select circuit) 241′, circuit 285_1 (directly above selectcircuit 241), and circuit 287_1 (directly below select circuit 241′).FIG. 2A shows an example of six memory cell strings and their associatedcircuits (e.g., top and bottom select circuits and top and bottom GIDLcurrent generator circuits) in each of blocks 203 ₀ and 203 ₁. Thenumber of memory cell strings and their associated select circuits andcurrent generator circuits in each of blocks 203 ₀ and 203 ₁ can vary.

Memory device 200 can include lines 270, 271, and 272 that carry signalsBL0, BL1, and BL2, respectively. Lines 270, 271, and 272 can correspondto data lines 170 of FIG. 1. In FIG. 2A, each of lines 270, 271, and 272can be structured as a conductive line and can form part of a respectivedata line (e.g., bit line) of memory device 200. The memory cell stringsof blocks 203 ₀ and 203 ₁ can share lines 270, 271, and 272. Forexample, memory cell strings 231, 232, 237, and 238 can share line 270.Memory cell strings 233, 234, 239, and 240 can share line 271. Memorycell strings 235, 236, 291, and 292 can share line 272. FIG. 2A showsthree lines (e.g., data lines) 270, 271, and 272 as an example. Thenumber of data lines can vary.

Memory device 200 can include a line 299 that can carry a signal SRC(e.g., source line signal). Line 299 can be structured as a conductiveline and can form part of a source (e.g., a source line) of memorydevice 200. Blocks 203 ₀ and 203 ₁ can share line 299.

Memory device 200 can include separate control lines in blocks 203 ₀ and203 ₁. As shown in FIG. 2A, memory device 200 can include control lines220 ₀, 221 ₀, 222 ₀, and 223 ₀ that can carry corresponding signals(e.g., word line signals) WL0 ₀, WL1 ₀, WL2 ₀, and WL3 ₀. Memory device200 can include control lines 220 ₁, 221 ₁, 222 ₁, and 223 ₁ that cancarry corresponding signals (e.g., word line signals) WL0 ₁, WL1 ₁, WL2₁, and WL3 ₁. FIG. 2A shows four control lines (220 ₀ through 223 ₀ or220 ₁ through 223 ₁) in each of blocks 203 ₀ and 203 ₁ as an example.The number of control lines can vary.

Control lines 220 ₀ through 223 ₀ and 220 ₁ through 223 ₁ can form partof respective access lines (e.g., similar to access lines 150 of FIG. 1)of memory device 200 to access memory cells in a respective block. Forexample, during a read or write operation to store information in orretrieve information from a memory cell (or memory cells) in block 203₀, control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀ can be activated (e.g.,provided with positive voltages) to access a selected memory cell (ormemory cells) in block 203 ₀. In memory device 200, blocks 203 ₀ and 203₁ (which share lines 270, 271, and 272) can be accessed (e.g., accessedduring a read or write operation) one block at a time. Thus, in theexample here, control lines 220 ₁, 221 ₁, 222 ₁, and 223 ₁ of block 203₁ can be deactivated (e.g., provided with zero volts (e.g., ground))when control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀ of block 203 ₀ areactivated.

As shown in FIG. 2A, memory device 200 can include double (e.g., upperand lower) drain select lines, including select lines 281 _(A), 282_(A), 283 _(A), and 284 _(A) (e.g., upper drain select lines) and selectlines 281 _(B), 282 _(B), 283 _(B), and 284 _(B), (e.g., lower drainselect lines). Each of select lines 281 _(A), 282 _(A), 283 _(A), and284 _(A) can carry a separate (e.g., different) signal (e.g., an upperselect line signal) SGD_(A). Each of select lines 281 _(B), 282 _(B),283 _(B), and 284 _(B) can carry a separate signal (e.g., a lower selectline signal) SGD_(B).

As shown in FIG. 2A, select circuits 241, 243, and 245 can share selectlines 281 _(A) and 281 _(B). Select circuits 242, 244, and 246 can shareselect line 282 _(A) and 282 _(B). Select circuits 247, 249, and 251 canshare select line 283 _(A) and 283 _(B). Select circuits 248, 250, and252 can share select line 284 _(A) and 284 _(B). Each of select circuits241 through 252 can include multiple select gates (e.g., multipletransistors, shown in FIG. 2B) that can be controlled (e.g., turned onor turned off) by two respective select lines (e.g., 281 _(A) and 281_(B), 282 _(A) and 282 _(B), 283 _(A) and 283 _(B), or 284 _(A) and 284_(B)).

Memory device 200 can include double (e.g., lower and upper) sourceselect lines, including select lines 281′_(A) and 283′_(A) (e.g., lowersource select lines) and select lines 281′_(B) and 283′_(B) (e.g., uppersource select lines). Each of select lines 281′_(A) and 283′_(A) cancarry a separate (e.g., different) signal SGS_(A). Each of select lines281′_(B) and 283′_(B) can carry a separate (e.g., different) signalSGS_(B). In an alternative arrangement of memory device 200, lines281′_(A) and 283′_(A) can carry the same signal, and lines 281′_(B) and283′_(B) can carry the same signal.

Select circuits 241′ through 246′ can share select lines 281′_(A) and281′_(B). Select circuits 247′ through 252′ can share select lines283′_(A) and 283′_(B). Each of select circuits 241′ through 252′ caninclude multiple select gates (e.g., multiple transistors, shown in FIG.2B) that can be controlled (e.g., turned on or turned off) by tworespective select lines (e.g., 281′_(A) and 281′_(B), or 283′_(A) and283′_(B)).

Each of circuits (e.g., top GIDL current generator circuits) 285_1,285_2, 285_3, and 285_4 can be coupled in series with a respectiveselect circuit (among select circuits 241 through 252) between arespective data line (one of lines 270, 271, and 272) and a respectivememory string (among memory cell strings 231 through 240, 291, and 292).Each of circuits 285_1, 285_2, 285_3, and 285_4 can include multipletransistors (shown in FIG. 2B).

As shown in FIG. 2A, memory device 200 can include lines 280_1 _(A),280_2 _(A), 280_3 _(A), and 280_4 _(A), each of which can carry aseparate (e.g., different) signal GG_(A). Memory device 200 alsoincludes lines 280_1 _(B), 280_2 _(B), 280_3 _(B), and 280_4 _(B), eachof which can carry a separate signal GG_(B). Lines 280_1 _(A), 280_2_(A), 280_3 _(A), 280_4 _(A), 280_1 _(B), 280_2 _(B), 280_3 _(B), and280_4 _(B) can be coupled to the gates of respective transistors (shownin FIG. 2B) of circuits 285_1, 285_2, 285_3, and 285_4. Thus, lines280_1 _(A), 280_2 _(A), 280_3 _(A), 280_4 _(A), 280_1 _(B), 280_2 _(B),280_3, and 280_4 _(B) can be called transistor gate lines.

As shown in FIG. 2A, circuits 285_1 can share lines 280_1 _(A) and 280_1_(B). Circuits 285_2 can share lines 280_2 _(A) and 280_2 _(B). Circuits285_3 can share lines 280_3 _(A) and 280_3 _(B). Circuits 285_4 canshare lines 280_4 _(A) and 280_4 _(B). Each of circuits 285_1, 285_2,285_3, and 285_4 can be controlled (e.g., turned on or turned off) bytwo respective transistor gate lines (e.g., 280_1 _(A) and 280_1 _(B),280_2 _(A) and 280_2 ₃, 280_3 _(A) and 280_3 _(B), or 280_4 _(A) and280_4 _(B)).

Each of circuits (e.g., bottom GIDL current generator circuits) 287_1,287_2, 287_3, and 287_4 can be coupled in series with a respectiveselect circuit (among select circuits 241′ through 252′) between line299 and a respective memory string (among memory cell strings 231through 240, 291, and 292). Each of circuits 287_1, 287_2, 287_3, and287_4 can include a transistor (shown in FIG. 2B).

As shown in FIG. 2A, memory device 200 can include lines 289_1 _(B) and289_3 _(B), each of which can carry a separate (e.g., different) signalGG′_(B). Lines 289_1 _(B) and 289_3 _(B) can be coupled to the gates ofrespective transistors (shown in FIG. 2B) of circuits 287_1, 287_2,287_3, and 287_4. Thus, lines 289_1 _(B) and 289_3 _(B) can be calledtransistor gate lines.

As shown in FIG. 2A, circuits 287_1 and 287_2 can share lines 289_1_(B). Circuits 287_3 and 287_4 can share lines 289_3 _(B). Each ofcircuits 287_1, 287_2, 287_3, and 287_4 can be controlled (e.g., turnedon or turned off) by a respective transistor gate line (e.g., 289_1 _(B)and 289_3 _(B)).

During an operation (e.g., read or write operation) of memory device200, signals GG_(A) and GG_(B) can be used to activate (e.g., turn on)respective circuits 285_1, 285_2, 285_3, and 285_4, and signal GG′_(B)can be used to activate (e.g., turn on) respective circuits 287_1,287_2, 287_3, and 287_4. Activating circuits 285_1, 285_2, 285_3, and285_4 can include providing (e.g., applying) voltages to signals GG_(A)and GG_(R). Activating circuits 287_1, 287_2, 287_3, and 287_4 caninclude providing (e.g., applying) voltages to signal GG′_(B).

The voltages provided to each of signal GG_(A), GG_(B), and GG′_(B) canhave different values for different operations of memory device 200. Forexample, the values of the voltages provided to signals GG_(A), GG_(B),and GG′_(B) during an erase operation can be much higher (e.g., twotimes or higher) than the values of the voltages provided to signalsGG_(A), GG_(B), and GG′_(B) during a read or write operation.

During an operation of memory device 200, one or both select circuitsassociated with a selected memory cell string can be activated (e.g., byturning on the transistors in the select circuits), depending on whichoperation memory device 200 performs on the selected memory cell string.During an operation of memory device 200, memory device 200 can select amemory cell of a particular memory cell string as a selected memory cellin order to store information in (e.g., during a write operation) or toretrieve information from (e.g., during a read operation) the selectedmemory cell. During an erase operation, memory device 200 can select ablock as a selected block to erase information from memory cells in aportion (e.g., a sub-block) of the selected block or memory cells fromthe entire selected block.

Activating a particular select circuit among select circuits 247 through252 during an operation of memory device 200 can include providing(e.g., applying) voltages having certain values to signals SGD_(A) andSGD_(B) associated with that particular select circuit. Activating aparticular select circuit among select circuits 247′ through 252′ caninclude providing (e.g., applying) voltages having certain values tosignals SGS_(A) and SGS_(B) associated with that particular selectcircuit. When a particular select circuit among select circuits 241through 252 is activated during a particular operation, it can couple(e.g., form a current path from) a selected memory cell stringassociated with that particular select circuit to a respective data line(e.g., one of lines 270, 271, or 272) through a respective circuit amongcircuits 285_1, 285_2, 285_3, and 285_4 (which is also activated duringthat particular operation). When a particular select circuit amongselect circuits 241′ through 252′ is activated, it can couple (e.g.,form a current path from) a selected memory cell string associated withthat particular select circuit to a source (e.g., line 299) through arespective circuit among circuits 287_1, 287_2, 287_3, and 287_4 (whichis also activated during that particular operation).

FIG. 2B shows a schematic diagram of memory device 200 of FIG. 2A,according to some embodiments described herein. For simplicity, FIG. 2Bshows labels for only four memory cell strings 231, 232, 237 and 238,eight select circuits 241, 242, 247, 248, 241′, 242′, 247′, and 248′,and labels for some of the top GIDL current generator circuits (e.g.,285_1, 285_2, 285_3, and 285_4) and some of the bottom GIDL currentgenerator circuits (e.g., 287_1, 287_2, 287_3, and 287_4).

As shown in FIG. 2B, memory device 200 can include memory cells 210,211, 212, and 213, select gates (e.g., drain select gates) 261 and 262and select gates (e.g., source select gates) 263 and 264 that can bephysically arranged in three dimensions (3-D), such as x, y, and zdimensions with respect to the structure (shown in FIG. 3) of memorydevice 200.

In FIG. 2B, each of the memory cell strings (e.g., strings 231, 232, 237and 238) of memory device 200 can include one of memory cells 210, oneof memory cells 211, one of memory cells 212, and one of memory cells213 coupled in series among each other. FIG. 2B shows an example wherememory device 200 has four levels (e.g., four tiers) of respectivememory cells 210, 211, 212, and 213 and four memory cells in each of thememory cell strings. The number of levels (e.g., tiers) of memory cellsof memory device 200 can vary. Thus, the number of memory cells in eachmemory cell string can also vary. Further, one skilled in the art wouldrecognize that some of the memory cells among memory cells 210, 211,212, and 213 of memory cell strings 231, 232, 237 and 238, may be dummymemory cells. Dummy memory cells are memory cells that are notconfigured to store information. Dummy memory cells may be configuredfor purposes known to those skilled in the art. In some examples ofmemory device 200, one or two (or more) of memory cells at the two endsof each memory cell strings 231, 232, 237 and 238 (e.g., memory cellsimmediately next to select gates 262, select gates 264, or both selectgates 262 and 264) may be dummy memory cells.

As shown in FIG. 2B, memory device 200 can include transistors 286 and288. Each of circuits 285_1, 285_2, 285_3, and 285_4 can include two oftransistors 286. Each of circuits 287_1, 287_2, 287_3, and 287_4 caninclude one of transistors 288. Each of transistors 286 and 288 canoperate as a switch during a read or write operation of memory device200. During a read or write operation, signals GG_(A), GG_(B), andGG′_(B) at particular current generator circuits (among circuits 285_1,285_2, 285_3, 285_4, 287_1, 287_2, 287_3, and 287_4) associated withselected memory cell strings of a selected block (e.g., block 203 ₀ or203 ₁) can be provided with voltages, such that transistors 286 and 288associated with those particular current generator circuits can beturned on. During an erase operation, signal GG_(A), GG_(B), and GG′_(B)of a selected block can be provided with voltages to cause transistors286 and 288 of the selected block to be in a condition such that GIDLcurrent can be generated to help improve the erase operation of memorydevice 200.

As shown in FIG. 2B, each of select circuits 241, 242, 247, and 248 caninclude two select gates (e.g., two drain select gates): one of selectgates 261 and one of select gates 262. Each of select circuits 241′,242′, 247′, and 248′ can include two select gates (e.g., two sourceselect gates): one of select gates 263 and one of select gates 264. Eachof select gates 261, 262, 263, and 264 can operate as a transistor. FIG.2B shows each of select gates 261, 262, 263, and 264 and transistors 286and 288 as having the same structure as memory cells 210, 211, 212, and213 as an example. In some examples of memory device 200, some or all ofselect gates 261, 262, 263, and 264 and transistors 286 and 288 can havea structure (e.g., a structure of a field effect transistor (FET))different from the structure of memory cells 210, 211, 212, and 213).

In memory device 200, a select line (e.g., a drain select line 281 _(A),282 _(A), 283 _(A), 284 _(A), 281 _(B), 282 _(B), 283 _(B), or 284 _(B),or a source select line 281′_(A), 281′, 283′_(A), or 283′_(B)) can carrya signal (e.g., signal SGD_(A), SGD_(B), SGS_(A), or SGS_(B)) but aselect line does not operate like a switch (e.g., a transistor). Aselect gate (e.g., a drain select gate 261 or 262 or a source selectgate 263 and 264) can receive a signal from a respective select line andcan operate like a switch (e.g., a transistor).

In this description, a line (e.g., any of drain select lines 281 _(A),282 _(A), 283 _(A), 284 _(A), 281 _(B), 282 _(B), 283 _(B), and 284_(B), any of source select lines 281′_(A), 281′, 283′_(A), and 283′, anyof transistor gate lines 280_1 _(A), 280_2 _(A), 280_3 _(A), 280_4 _(A),280_1 _(B), 280_2 _(B), 280_3 _(B), 280_4 _(B), 289_1 _(A), 289_3 _(A)(FIG. 5A), 289_1, and 289_3 _(B), and any of control lines 220 ₀ through223 ₀ and 220 ₁ through 223 ₁) includes a piece of conductive material,a region of conductive material, a layer of conductive material, or anyshape of a structure that can carry an electrical signal. Thus, in thisdescription, a line includes a “line” shape structure and any otherstructural shapes (e.g., a region of any shape, a layer shape, and othershapes).

In order to focus on the embodiments discussed herein, the descriptionbelow with reference to FIG. 2C and FIG. 2D focuses on four memory cellstrings 231, 232, 237, and 238, select circuits 241, 242, 247, 248,241′, 242′, 247′, and 248′, some of the current generators circuits(e.g., circuits 285_1, 285_2, 285_3, 285_4, 287_1, 287_2, 287_3, and287_4). Other memory cell strings, select circuits, and currentgenerator circuits of memory device 200 have similar structures andconnections.

FIG. 2C shows a schematic diagram of a portion of memory device 200 ofFIG. 2B including line 270, circuits 285_1, 285_2, 285_3, 285_4, selectcircuits 241, 242, 247, and 248, memory cell strings 231, 232, 237, and238, select circuits 241′, 242′, 247′, and 248′, circuits 287_1, 287_2,287_3, and 287_4, and line 299, according to some embodiments describedherein. As shown in FIG. 2C, select gates 261 and 262 of each of selectcircuits 241, 242, 247, and 248 can be coupled in series with two oftransistors 286 between line 270 and a respective memory cell stringamong memory cell strings 231, 232, 237, and 238. Select gates 263 and264 of each of select circuits 241′, 242′, 247′, and 248′ can be coupledin series with a transistor among transistors 288 between line 299 and arespective memory cell string among memory cell strings 231, 232, 237,and 238.

Select gate 261 of select circuit 241 has a terminal (e.g., a transistorgate) that can be part of (e.g., formed by a portion of) select line 281_(A). Select gate 262 of select circuit 241 has a terminal (e.g., atransistor gate) that can be part of (e.g., formed by a portion of)select line 281 _(B). Select gates 261 and 262 of select circuit 241 canbe controlled (e.g., turned on or turned off) by signals SGD_(A) andSGD_(B) provided to select lines 281 _(A) and 281 _(B), respectively.

Select gate 263 of select circuit 241′ has a terminal (e.g., atransistor gate) that can be part of (e.g., formed by a portion of)select line 281′_(A). Select gate 264 of select circuit 241′ has aterminal (e.g., a transistor gate) that can be part of (e.g., formed bya portion of) select line 281′_(B). Select gates 263 and 264 of selectcircuit 241′ can be controlled (e.g., turned on or turned off) bysignals SGS_(A) and SGS_(B) provided to select lines 281′_(A) and281′_(B), respectively.

Similarly, as shown in FIG. 2C, select gates 261 and 262 of each ofselect circuits 242, 247, and 248 also have terminals (transistor gates)that can be parts of (e.g., formed by portions of) respective selectlines among select lines 282 _(A), 283 _(A), 284 _(A), 282 _(B), 283_(B), and 284 _(B). Select gates 263 and 264 of each of select circuits242′, 247′, and 248′ also have terminals (transistor gates) that can bepart of (e.g., formed by a portions of) respective select lines amongselect lines 281′_(A), 283′_(A), 281′_(B), and 283′_(B).

Each of transistors 286 and 288 has a terminal (e.g., a transistor gate)that can be part of (e.g., formed by a portion of) a respectivetransistor gate line. For example, transistor 286 of circuit 285_1associated with signal GG_(A) has a transistor gate that can be part ofline (e.g., transistor gate line) 280_1 _(A). In another example,transistor 286 of circuit 285_1 associated with signal GG_(B) has atransistor gate that can be part of line (e.g., transistor gate line)280_1 _(B). In a further example, transistor 288 of circuit 287_1 has atransistor gate that can be part of line (e.g., transistor gate line)289_1 _(B).

During an operation (e.g., a read or write operation) of memory device200, select gates 261, 262, 263, and 264 and transistors 286 and 288 ofparticular select circuits associated with a selected memory cell stringcan be selectively activated (e.g., turned on) to couple the selectedmemory cell string to a respective data line (e.g., line 270, 271, or272) and the source (e.g., line 299). For example, in FIG. 2C, during awrite operation of memory device 200, if memory cell string 231 is aselected memory cell string, then select gates 261 and 262 of selectcircuit 241, transistors 286 of circuits 285_1, and transistor 288 ofcircuit 287_1 can be activated to couple memory cell string 231 to line270; select gates 263 and 264 of select circuit 241′ may not beactivated in this example.

In another example, in FIG. 2C, during a read operation of memory device200, if memory cell string 231 is a selected memory cell string, thenselect gates 261 and 262 of select circuit 241 and transistors 286 ofcircuits 285_1, and transistor 288 of circuit 287_1 can be activated tocouple memory cell string 231 to line 270; select gates 263 and 264 ofselect circuit 241′ can also be activated in this example to couplememory cell string 231 to line 299. In these two examples here, whilememory cell string 231 is selected, memory cell strings 232, 237, and238 can be deselected. Thus, select gates 261, 262, 263, and 264 inselect circuits 242, 247, 248, 242′, 247′, and 248′ (associated withmemory cell strings 232, 237, and 238 that are deselected) andtransistors 286 of circuits 285_2, 285_3, and 285_4 can be deactivated(e.g., turned off) to decouple memory cell strings 232, 237, and 238from line 270 and line 299.

In an erase operation of memory device 200, signals SGD_(A), SGD_(B),SGS_(A), and SGS_(B) on respective drain and source select gates of aselected block (a block selected to erase information from it) can beprovided with voltages having values much higher than the values ofvoltages provided to these signals during a read or write operation(example values shown in FIG. 2D). As described above with reference toFIG. 2A, signals GG_(A), GG_(B), and GG′_(B) on respective transistorgate lines of a selected block can be provided with voltages havingvalues much higher than the values of voltages provided to the thesesignals during a read or write operation (example values shown in FIG.2D). In a deselected block of memory device 200 during read, write, anderase operations, the signals in the deselected block can bedeactivated.

FIG. 2D shows example waveforms of signals BL0, BL1, BL2, GG_(A),GG_(B), SGD_(A), SGD_(B), SGS_(A), SGS_(B), GG′_(B), and SRC of memorydevice 200 (FIG. 2A through FIG. 2C) during example erase, write, andread operations, according to some embodiments described herein. SignalsSGD_(A), SGD_(B), SGS_(A), and SGS_(B) shown in FIG. 2D are associatedwith a block (e.g., either block 203 ₀ or block 203 ₁) of memory device200 that is selected during the example erase, write, and readoperations. FIG. 2D omits other signals (e.g., some of signals shown inFIG. 2C) of memory device 200 to help focus on the embodiments of thememory device described herein. During erase, write, and read operationsof memory device 200, the omitted signals can be provided with voltageshaving values known to those skilled in the art.

The specific values of the voltages associated with erase, write, andread operations shown in FIG. 2D and in this description here areexample values. Other voltage values may be used.

The following description refers to FIG. 2B, FIG. 2C, and FIG. 2D. InFIG. 2D, each of voltages V_(ERASE) can have a value greater than thevalue of each of voltages V1 through V12, V_(PreCh), V_(BL), and V0.Voltage V0 can be 0V (e.g., ground potential, such as Vss). Each ofvoltages V1 through V12 can have a positive value (e.g., a value greaterthan the value of voltage V0). Voltage V_(ERASE) can have a value ofapproximately 20V. Voltage V1 can be either voltage Vcc (e.g., a supplyvoltage of memory device 200) or voltage Vpass. Voltage Vcc can have avalue of approximately between 1V and 3V (or other values). VoltageVpass can have a value that can cause unselected memory cells of aselected memory cell string to operate as an active conductive path(e.g., to conduct current) during a read or write operation. VoltageVpass can have a value of approximately 3V to 5V (or other values).Voltage V_(PreCh) can have a value between 0.5V up to the value ofvoltage Vcc. Each of voltages V2 through V7 can have a value equal tothe value of voltage Vcc or other values to turn on respective drainselect gates (e.g., 261 and 262 in FIG. 2C) and source select gates(e.g., 263 and 264 in FIG. 2C) during write and read operations.Voltages V8, V9, and V10 can have the same value. Voltages V11 and V12can have the same value. As an example, when voltage V_(ERASE) has avalue of approximately 20V, each of voltages V8, V9, and V10 can have avalue of approximately 10V, and each of voltages V11 and V12 can have avalue of approximately 15V.

During the write operation, voltage V_(BL) can have a value that dependson the value (e.g., value of a bit) of information to be stored in aselected memory cell. During the read operation, voltage V_(BL) can havea value that depends on the value (e.g., value of a bit) of informationsensed from a selected memory cell.

As shown in FIG. 2D, during the erase operation, signals BL0, BL1, andBL2 and SRC can be provided with a voltage V_(ERASE) to eraseinformation stored in memory cells 210, 211, 212, and 213 of the memorystrings of a selected block (e.g., block 203 ₀ or block 203 ₁ in FIG.2C). Transistors 286 and 288 (FIG. 2C) can operate to generate GIDLcurrent (e.g., operate as GIDL current generators) to help the eraseoperation. For example, the GIDL current generated by transistors 286and 288 during the erase operation may speed up the charging of the bodyof the memory cell strings in the selected block.

As shown in FIG. 2D, the write operation of memory device 200 can havedifferent stages, such as a write precharge stage (shown as “PreCh”during the write operation in FIG. 2D) and a program stage (shown as“Prgm” in FIG. 2D) after the write precharge stage. During the writeprecharge stage, signals BL0, BL1, and BL2 can be provided withprecharge voltage V_(PreCh). During the program stage, signals BL0, BL1,and BL2 can have voltage V_(BL), V0, or a voltage having a value betweenthe values of voltages V0 and V_(BL), depending on the value ofinformation to be stored in a selected memory cell of a memory cellstring coupled to a respective line among lines 270, 271, and 272(associated with signals BL0, BL1, and BL2). During the write operation,signals GG_(A), GG_(B), and GG′_(B) can be provided with voltage V1,such that transistors 286 and 288 (FIG. 2C) can be activated (e.g.,turned on); and signal SRC can be provided with voltage V1 (e.g., Vcc).During the write operation, signals SGD_(A) and SGD_(B) can be providedwith voltages V2 and V3, respectively, and signals SGS_(A) and SGS_(B)can be provided with voltage V0.

The read operation of memory device 200, as shown in FIG. 2D, can havedifferent stages, such as a read precharge stage (shown as “PreCh”during a read operation in FIG. 2D) and a sense stage (shown as “Sense”in FIG. 2D) after the read precharge stage. During the read prechargestage, signals BL0, BL1, and BL2 can be provided with precharge voltageV_(PreCh). During the sense stage, signals BL0, BL1, and BL2 can havevoltage V_(B) or V0, depending on the value of information sensed from aselected memory cell of a memory cell string coupled to a respectiveline among lines 270, 271, and 272 (associated with signals BL0, BL1,and BL2). During the read operation, signals GG_(A), GG_(B), and GG′_(B)can be provided with voltage V1, such that transistors 286 and 288 (FIG.2C) can be activated (e.g., turned on); and signal SRC can be providedwith voltage V0. During the read operation, signals SGD_(A) and SGD_(B)can be provided with voltages V4 and V5, respectively; and signalsSGS_(A) and SGS_(B) can be provided with voltages V6 and V7,respectively.

FIG. 3 shows a side view of a structure of a portion of memory device200, according to some embodiments described herein. The structure ofmemory device 200 in FIG. 3 corresponds to part of the schematic diagramof memory device 200 shown in FIG. 2C. For simplicity, FIG. 3 shows thestructure of memory device 200 that includes line 270 (and associatedsignal BL0), circuit (e.g., current generator circuit) 285_1, selectcircuit 241, memory cell string 231, control lines 220 ₀, 221 ₀, 222 ₀,and 223 ₀, select circuit 241′, and circuit (e.g., current generatorcircuit) 287_1. Other similar elements of memory device 200 in FIG. 2A,FIG. 2B, and FIG. 2C can have structures such as the ones shown in FIG.3.

As shown in FIG. 3, memory device 200 can include a substrate 390 overwhich memory cells 210, 211, 212, and 213 of memory cell string 231 canbe formed (e.g., formed vertically with respect to substrate 390).Memory device 200 includes different levels 307 through 317 with respectto a z-dimension. Levels 307 through 317 are internal device levelsbetween substrate 390 and line 270 of memory device 200.

As shown in FIG. 3, memory cells 210, 211, 212, and 213 can be locatedin levels 310, 311, 312, and 313, respectively. Control lines 220 ₀, 221₀, 222 ₀, and 223 ₀ (associated with memory cells 210, 211, 212, and213, respectively) can also be located in levels 310, 311, 312, and 313,respectively.

Select lines 281 _(A) and 281 _(B) can be located in different levels(e.g., levels 315 and 314, respectively), such that memory cell string231 is between select lines 281 _(A) and 2818 and substrate 390. Selectlines 281′_(A) and 281′_(B) can be located in different levels (e.g.,levels 308 and 309, respectively) between substrate 390 and memory cellstring 231.

Lines (e.g., transistor gate lines) 280_1 _(A) and 280_1 _(B) can belocated in different levels (e.g., levels 317 and 316, respectively),such that select lines 281 _(A) and 281 _(B) are between lines 280_1_(A) and 280_1 _(B) and memory cell string 231. Line (e.g., transistorgate line) 289_1 _(B) can be located in level 307, such that line 289_1_(B) is between select lines 281′_(A) and 281′_(B) and substrate 390.

Substrate 390 of memory device 200 can include monocrystalline (alsoreferred to as single-crystal) semiconductor material. For example,substrate 390 can include monocrystalline silicon (also referred to assingle-crystal silicon). The monocrystalline semiconductor material ofsubstrate 390 can include impurities, such that substrate 390 can have aspecific conductivity type (e.g., n-type or p-type). Although not shownin FIG. 3, substrate 390 can include circuitry that can be located undermemory array 201 (FIG. 2A), such as located directly under line 299 inFIG. 3. Such circuitry can include sense amplifiers, buffers (e.g., pagebuffers), decoders, and other circuit components of memory device 200.

As shown in FIG. 3, line 270 can have a length extending in thedirection of an x-dimension, which is perpendicular to the z-dimensionand perpendicular to the y-dimension. Line 270 can include a conductivematerial (e.g., conductively doped polycrystalline silicon (dopedpolysilicon), metals, or other conductive materials). Line 299 caninclude a conductive material. FIG. 3 shows an example where line 299(e.g., source) can be formed over a portion of substrate 390 (e.g., bydepositing a conductive material over substrate 390). Alternatively,line 299 can be formed in or formed on a portion of substrate 390 (e.g.,by doping a portion of substrate 390).

As shown in FIG. 3, memory device 200 can include a pillar 331 having alength extending outwardly (e.g., vertically in the direction of thez-dimension of memory device 200) from a conductive material region ofline 299. Pillar 331 can include portions 343, 344, 345, and 346.

Portion 343 (conductive portion) of pillar 331 has length extending inthe direction (in the z-dimension) of the length of pillar 331 and canbe coupled (e.g., directly coupled) to line 270. For example, thematerial of portion 343 can directly contact a conductive materialregion (a portion of) line 270. Portion 343 can be called a plug (e.g.,a conductive plug) of pillar 331. As described in more detail below,including portion 343 and circuit 285_1 (which includes transistors 286)may improve operations (e.g., erase operation) of memory device 200 oversome conventional memory devices.

Portion 346 (conductive portion) of pillar 331 (FIG. 3) can be coupled(e.g., directly coupled) to line 299. For example, the material ofportion 346 can directly contact a conductive material region (a portionof) of line 299.

Portion 344 of pillar 331 has length extending in the direction (in thez-dimension) of the length of pillar 331 and can be between (e.g.,vertically between) portions 343 and 346. Portion 344 and at least partof each of portions 343 and 346 can form a conductive channel (e.g.,part of the body of memory cell string 231) in pillar 331. Theconductive channel (formed at least by portion 344) has length extendingin the direction (in the z-dimension) of the length of pillar 331 andcan carry current (e.g., current between line 270 and line 299 (e.g.,source)) during an operation (e.g., read, write, or erase) of memorydevice 200.

Portion 345 (dielectric portion) of pillar 331 can be surrounded (e.g.,horizontally surrounded) by portions 344 and 346. During a process offorming pillar 331 of memory device 200, pillar 331 can have a hollowcore (e.g., an empty core) before portion 345 is formed. Portion 345 inFIG. 3 can include a dielectric material (e.g., silicon dioxide) thatoccupies (e.g., fills) the hollow core (as shown in FIG. 3), such thatportion 344 can surround at least part of portion 345.

Each of portions 343, 344, and 346 can include conductive material(e.g., doped polycrystalline silicon). Portions 343, 346, and 344 caninclude materials of the same conductivity type but different dopingconcentrations. For example, portions 343, 346, and 344 can include asemiconductor material of n-type (e.g., n-type polycrystalline silicon),but each of portions 343 and 346 can have a doping concentration (n-typeimpurities (e.g., arsenic or phosphorous)) higher than the dopingconcentration (n-type impurities (e.g., arsenic or phosphorous)) ofportion 344.

Alternatively, portions 343 and 346 can include materials of the sameconductivity type, and portion 344 can include a material having adifferent conductivity type from that of portions 343 and 346. Forexample, portions 343 and 346 can include a semiconductor material ofn-type (e.g., n-type polycrystalline silicon), and portion 344 caninclude a semiconductor material of p-type (e.g., p-type polycrystallinesilicon). Each of portions 343 and 346 can have a doping concentration(n-type impurities (e.g., arsenic or phosphorous)) higher than thedoping concentration (e.g., p-type impurities (e.g., boron)) of portion344.

As shown in FIG. 3, memory device 200 includes an interface 348 inpillar 331. Interface 348 is the location where portion 343 (e.g., thebottom of the material of portion 343) contacts portion 345 (e.g.,contact the top of the material of portion 345). FIG. 3 shows an examplewhere interface 348 (e.g., the bottom of portion 343) is located (e.g.,positioned) at approximately level 316. However, interface 348 can belocated (e.g., positioned) at another location in pillar 331 (e.g., at alocation between level 315 and 317). As described below with referenceto FIG. 4, the structure of memory device 200 can allow its operations(e.g., erase operation) to be less susceptible to process variations(process of forming memory device 200), thereby suppressing the effectof process variations on operations of memory device 200. This allowsmemory device 200 to maintain its operations even if the location ofinterface 348 may deviate from its intended location (e.g., due toprocess variations). The structure of memory device 200 can also allowit to generate a relatively higher amount of erase GIDL current thatfurther helps erase operations of memory device 200.

As shown in FIG. 3, memory cells 210, 211, 212, and 213 of memory cellstring 231 can be located along a segment of pillar 331 (e.g., thesegment of pillar 331 extending from level 310 to level 313). Controllines 220 ₀, 221 ₀, 222 ₀, 223 ₀ (associated with respective memorycells 210, 211, 212, and 213) can also be located along a segment (e.g.,the segment extending from level 310 to level 313) of pillar 331. Thematerials of control lines 220 ₀, 221 ₀, 222 ₀, 223 ₀ can include aconductive material (e.g., conductively doped polycrystalline silicon ofn-type, metals, or other conductive materials).

Transistor 286 associated with line (e.g., transistor gate line) 280_1_(A) can be located in level 317 along a segment (segment at level 317)of pillar 331. Line 280_1 _(A) can also be located in level 317 along asegment (segment at level 317) of pillar 331.

Transistor 286 associated with line (e.g., transistor gate line) 280_1_(B) can be located in level 316 along a segment (segment at level 316)of pillar 331. Line 280_1 _(B) can also be located in level 316 along asegment (segment at level 316) of pillar 331.

Select line 281 _(A) can be located in level 315 along a segment(segment at level 315) of pillar 331. Select line 281 _(B) can belocated in level 314 along a segment (segment at level 314) of pillar331.

Select line 281′_(B) can be located in level 309 along a segment(segment at level 309) of pillar 331. Select line 281′_(A) can belocated in level 308 along a segment (segment at level 308) of pillar331.

Transistor 288 associated with line (e.g., transistor gate line) 289_1_(B) can be located in level 307 along a segment (segment at level 307)of pillar 331. Line 289_1 _(B) can also be located in level 307 along asegment (segment at level 307) of pillar 331.

The materials of lines 280_1 _(A), 280_1 _(B), and 289_1 _(B) and selectlines 281 _(A), 281 _(B), 281′A, and 281′_(B) can include conductivelydoped polycrystalline silicon, metals, or other conductive materials.The materials of lines 280_1 _(A), 280_1, and 289_1 _(B) and selectlines 281 _(A), 281 _(B), 281′_(A), and 281′_(B) can be the same as theconductive material of control lines 220 ₀, 221 ₀, 222 ₀, 223 ₀.

As shown in FIG. 3, memory device 200 can include a structure 330, whichincludes portions 301, 302, and 303 between pillar 331 and control lines220 ₀, 221 ₀, 222 ₀, 223 ₀. Each of memory cells 210, 211, 212, and 213of memory cell string 231 can include part of structure 330 (part ofportions 301, 302, and 303 at respective levels 310, 311, 312, and 313).For example, part of portion 302 at a particular memory cell amongmemory cells 210, 211, 212, and 213 can be a charge storage structure(e.g., a memory portion) of that particular memory cell and can beconfigured to store information in that particular memory cell.

Structure 330 can be part of a TANOS (TaN, Al₂O₃, Si₃N₄, SiO₂, Si)structure. For example, portion 301 (e.g., interpoly dielectrics) caninclude a charge blocking material or materials (e.g., a dielectricmaterial such as TaN and Al₂O₃) that are capable of blocking a tunnelingof a charge. Portion 302 can include a charge storage element (e.g.,charge storage material or materials, such as Si₃N₄ or other dielectricmaterials) that can provide a charge storage function (e.g., trapcharge) to represent a value of information stored in memory cells 210,211, 212, or 213. Thus, in this example, the charge storage structure(part of portion 302) in each of memory cells 210, 211, 212, and 213that is configured to store information is a dielectric structure, whichcan include a dielectric material (e.g., Si₃N₄). Portion 303 can includea tunnel dielectric material or materials (e.g., SiO₂) that are capableof allowing tunneling of a charge (e.g., electrons). As an example,portion 303 can allow tunneling of electrons from portion 344 to portion302 during a write operation and tunneling of electrons from portion 302to portion 344 during an erase operation of memory device 200.

In an alternative arrangement of memory device 200, structure 330 can bepart of a SONOS (Si, SiO₂, Si₃N₄, SiO₂, Si) structure. In thisalternative arrangement, in each of memory cells 210, 211, 212, and 213,the memory portion (part of portion 302) can be a dielectric material(e.g., Si₃N₄) portion.

In another alternative arrangement of memory device 200, structure 330can be part of a floating gate structure. In this alternativearrangement, the charge storage structure (part of portion 302) in eachof memory cells 210, 211, 212, and 213 that is configured to storeinformation can be a polycrystalline silicon structure.

As shown in FIG. 3, a select line (e.g., 281 _(A), 281 _(B), 281′_(A),or 281′_(B)) is a piece (e.g., a single layer) of conductive material(e.g., polycrystalline silicon, metal, or other conductive materials).As described above, a select line can carry a signal (e.g., signalSGD_(A), SGD_(B), SGS_(A), or SGS_(B) in FIG. 2C) but it does notoperate like a switch (e.g., a transistor). A select gate (e.g., each ofselect gates 261, 262, 263, and 264) can include a portion of arespective select line (e.g., a portion of the piece of the conductivematerial that forms the respective select line) and additionalstructures to perform a function (e.g., function of a transistor). Forexample, in FIG. 3, select gate 261 can include a portion of select line281 _(A) and a portion of structure 330, select gate 262 can include aportion of select line 281 _(B) and a portion of structure 330, selectgate 263 can include a portion of select line 281′_(A) and a portion ofstructure 330, and select gate 264 can include a portion of select line281′_(B) and portion of structure 330.

Similarly, as shown in FIG. 3, a transistor gate line (e.g., 280_1 _(A),280_1, or 289_1 _(B)) is a piece (e.g., a single layer) of conductivematerial (e.g., polycrystalline silicon, metal, or other conductivematerials). A transistor gate line can carry a signal (e.g., signalGG_(A), GG_(B), or GG′_(B) in FIG. 2C) but a transistor gate line doesnot operate like a switch (e.g., a transistor). A transistor (e.g., eachof transistors 286 and 288) associated with a transistor gate line(e.g., 280_1 _(A), 280_1 _(B), or 289_1 _(B)) can include a portion of arespective transistor gate line (e.g., a portion of the piece of theconductive material that forms the respective transistor gate line) andadditional structures to perform a function of a transistor. Forexample, in FIG. 3, transistors 286 can include respective portions oflines 280_1 _(A) and 280_1 _(B) and respective portions of structure330, and transistor 288 can include a portion of line 289_1 _(B) and aportion of structure 330.

FIG. 3 shows an example where transistors 286 and 288 and select gates261, 262, 263, and 264 have the same structure (e.g., TANOS structure)as memory cells 210, 211, 212, and 213. Alternatively, some or all oftransistors 286 and 288 and select gates 261, 262, 263, and 264 can havea different structure, such as an FET structure. An example of an FETincludes a metal-oxide semiconductor (MOS) transistor structure. As isknown to those skilled in the art, an FET usually includes a transistorgate, a transistor body channel, and a gate oxide between the transistorgate and the transistor body channel that can be in direct contact withthe transistor gate and the transistor body channel.

As shown in FIG. 3, two adjacent control lines (two control lineslocated immediately vertically next to each other in the direction ofthe z-dimension) among control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀ arevertically separated from each other by a distance (e.g., spacing) D1.Select lines 281 _(A) and 281 _(B) are vertically separated from eachother by a distance (e.g., spacing) D2. Select lines 281′_(A) and281′_(B) are vertically separated from each other by a distance (e.g.,spacing) D2′. Distances D2 and D2′ can be the same (e.g., substantiallyequal). Each of distances D2 and D2′ can be the same as distance D1.

Lines 280_1 _(A) and 280_1 are vertically separated from each other by adistance (e.g., spacing) D3. Line 280_1 _(B) can be vertically separatedfrom select line 281 _(A) by a distance (e.g., spacing) D4. Line 289_1_(B) can be vertically separated from select line 281′_(A) by a distance(e.g., spacing) D4′. Each of distances D3, D4, and D4′ can be the sameas distance D1. Thus, as described above, distances (e.g., verticaldistances) D1, D2, D2′, D3, D4, and D4′ can be the same.

As shown in FIG. 3, distance D1 is a vertical distance (e.g., verticalspacing) measured from the nearest top or bottom edge (surfaces directlyfacing each other with respect to the z-dimension) of any of twovertically adjacent control lines. As described above, each of controllines 220 ₀, 221 ₀, 222 ₀, and 223 ₀ can be formed from a conductivematerial (e.g., metal or another conductive material). Thus, distance D1can be measured between two nearest edges of the materials that form twoadjacent control lines. For example, distance D1 can be measured fromthe nearest edges of the materials that form control lines 220 ₀ and 221₀, the nearest edges of the materials that form control lines 221 ₀ and222 ₀, or the nearest edges of the materials that form control lines 222₀ and 223 ₀.

Distance D2 is a vertical distance (e.g., vertical spacing) measuredfrom the nearest top or bottom edge (surfaces directly facing each otherwith respect to the z-dimension) of select lines 281 _(A) and 281 _(B).As described above, select lines 281 _(A) and 281 _(B) can be formedfrom a conductive material (e.g., metal or another conductive material).Thus, distance D2 can be measured between two nearest edges of thematerials that form select lines 281 _(A) and 281 _(B).

Distance D2′ is a vertical distance (e.g., vertical spacing) measuredfrom the nearest top or bottom edge (edges with respected to thez-dimension sides directly facing each other with respect to thez-dimension) of select lines 281′_(A) and 281′_(B). As described above,select lines 281′_(A) and 281′_(B) can be formed from a conductivematerial (e.g., metal or another conductive material). Thus, distanceD2′ can be measured between two nearest edges of the materials that formselect lines 281′_(A) and 281′_(B).

FIG. 3 also shows distance D1′ and D1″ between elements in memory device200. Distance D1′ is a vertical distance (e.g., vertical spacing)between the select line (e.g., select line 281 _(B) in this example)that is nearest to control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀, and thecontrol line (e.g., 223 ₀) that is nearest to select lines 281 _(A) and281 _(B)(nearest to select line 281 _(B) in this example). Thus,distance D1′ can be measured between two nearest edges of the materialsthat form select line 281 _(B) and control line 223 ₀. Distance D1″ is avertical distance (e.g., vertical spacing) between the select line(e.g., select line 281′_(B) in this example) that is nearest to controllines 220 ₀, 221 ₀, 222 ₀, and 223 ₀ and the control line (e.g., 220 ₀)that is nearest to select lines 281′_(A), and 281′_(B) (nearest toselect line 281′_(B) in this example). Thus, distance D1″ can bemeasured between two nearest edges of the materials that form selectline 281′_(B) and control line 220 ₀.

Distance D3 is a vertical distance (e.g., vertical spacing) measuredfrom the nearest top or bottom edge (surfaces directly facing each otherwith respect to the z-dimension) of lines 280_1 _(A) and 280_1 _(B). Asdescribed above, select lines 280_1 _(A) and 280_1 _(B) can be formedfrom a conductive material (e.g., metal or another conductive material).Thus, distance D3 can be measured between two nearest edges of thematerials that form lines 280_1 _(A) and 280_1 _(B).

Distance D4 is a vertical distance (e.g., vertical spacing) measuredfrom the nearest top or bottom edge (surfaces directly facing each otherwith respect to the z-dimension) of lines 281 _(A) and 280_1 _(B). Thus,distance D4 can be measured between two nearest edges of the materialsthat form lines 281 _(A) and 280_1 _(B).

Distance D4′ is a vertical distance (e.g., vertical spacing) measuredfrom the nearest top or bottom edge (surfaces directly facing each otherwith respect to the z-dimension) of lines 281′_(A) and 289_1 _(B). Thus,distance D4′ can be measured between two nearest edges of the materialsthat form lines 281′_(A) and 289_1 _(B).

As shown in FIG. 3, control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀, selectlines 281 _(A), 281 _(B), 281′_(A), and 281′, and lines 280_1 _(A),280_1 _(B), and 289_1 _(B) are separated from portion 344 (e.g., aconductive channel) of pillar 331 by the same distance Dx (e.g., ahorizontal distance with respect to the x-dimension). Distance Dx can bethe thickness of structure 330 with respect to the x-dimension.

As shown in FIG. 3, each of control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀has a thickness T1 in the z-dimension. Thickness T1 is a verticalthickness of the material of a respective control line among controllines 220 ₀, 221 ₀, 222 ₀, and 223 ₀. Each of select lines 281 _(A) and281 _(B) has a thickness T2 in the z-dimension. Thickness T2 is avertical thickness of the material of each of select lines 281 _(A) and281 _(B). Each of select lines 281′_(A) and 281′_(B) has a thickness T2′in the z-dimension. Thickness T2′ is a vertical thickness of thematerial of each of select lines 281′_(A) and 281′_(B).

Each of lines 280_1 _(A) and 280_1 _(B) has a thickness T3 in thez-dimension. Thickness T3 is a vertical thickness of the material ofeach of lines 280_1 _(A) and 280_1 _(B). Line 289_1 _(B) has a thicknessT3′ in the z-dimension. Thickness T3′ is a vertical thickness of thematerial of each of line 289_1 _(B).

Thicknesses T1, T2, T2′, T3, and T3′ can be the same (e.g.,substantially equal). Alternatively, thicknesses T2 and T2′ can be thesame (e.g., substantially equal), thicknesses T3 and T3′ can be the same(e.g., substantially equal), and each of thicknesses T2, T2′, T3, andT3′ can be different from thickness T1.

As shown in FIG. 3, memory device 200 can include a dielectric (e.g., anoxide of silicon) 355 located between elements of memory device 200. Forexample, dielectric 355 can be located (e.g., occupy the space) betweentwo adjacent control lines among control lines 220 ₀, 221 ₀, 222 ₀, and223 ₀. Thus, distance D1 can be the thickness of the material (e.g., anoxide of silicon) of a respective dielectric (e.g., dielectric 355)between two adjacent control lines among control lines 220 ₀, 221 ₀, 222₀, and 223 ₀. Similarly, each of distances D1′, D1″, D2, D2′, D3, D4,and D4′ can be the thickness of the material of a respective dielectric(e.g., dielectric 355) between two adjacent elements as shown in FIG. 3.

Providing the structure of memory device 200 (e.g., transistor gatelines 280_1 _(A), 280_1 _(B), and 289_1 _(B) and associated transistors286 and 288) as shown in FIG. 3 and operating it in ways as describedabove (e.g., FIG. 2D) allows memory device 200 to improve itsoperations. For example, GIDL current generated during an eraseoperation of memory device 200 may be improved (e.g., increased) withthe inclusion of line 280_1 _(A) and transistors 286 in memory device200 in comparison with memory device 200 without the inclusion of line280_1 _(A) and transistors 286.

Further, by making thicknesses T1, T2, T2′, T3, and T3′ of thecomponents (shown in FIG. 3) of memory device 200 the same, a simplifiedprocess of making memory device 200 can be achieved. For example, memorydevice 200 can be formed (e.g., fabricated) to provide improved GIDLcurrent for its erase operations without modifying the thickness (e.g.,T3 or T3′) of one or more of lines 280_1 _(A), 280_1 _(B), and 289_1_(B) (e.g., transistor gate lines in FIG. 3) to be different from (e.g.,greater than) the thickness (e.g., T1) of control lines 220 ₀, 221 ₀,222 ₀, and 223 ₀. In an alternative structure of memory device 200, thethickness of one or more of lines 280_1 _(A), 280_1 _(B), and 289_1 _(B)can be made greater than the thickness of control lines 220 ₀, 221 ₀,222 ₀, and 223 ₀. However, such an alternative structure may causeforming memory device 200 to be more complicated than forming thestructure of memory device 200 of FIG. 3 (where thicknesses T1, T2, T2′,T3, and T3′ are the same).

Moreover, as is known to those skilled in the art, process variationscan affect (e.g., degrade) the operations of a memory device. However,the structure of memory device 200 (FIG. 3) can allow its operations(e.g., erase operation) to be less susceptible to process variations(process of forming memory device 200). This means that memory device200 can have a relatively higher tolerance for process variations incomparison with memory device 200 without some of its components (e.g.,without the inclusion of line 280_1 _(A) and transistors 286 associatedwith line 280_1 _(A)). Additionally, the inclusion of line 280_1 _(A)and transistors 286 associated with line 280_1 _(A) allows operations(e.g., erase operations) of memory device 200 to be less susceptible tovariations in doping concentration of dopants (e.g., n-type impurities)used to form portion 343, portion 346, or both.

FIG. 4 is a graph showing an example relationship between the location(e.g., position) of interface 348 and erase GIDL current generatedduring an erase operation and of memory device 200 of FIG. 3, accordingto some embodiments described herein. The following description refersto FIG. 3 and FIG. 4. In FIG. 4, a reference location L_(REF) canrepresent an intended (e.g., desired) location for interface 348 inmemory device 200 at which erase GIDL current is expected (e.g., basedon design simulation) to be at an intended amount (e.g., a desiredamount) for an erase operation of memory device 200. As an example,reference location L_(REF) of interface 348 can be the location inpillar 331 at level 316 as shown in FIG. 3.

In FIG. 4, the arrow showing a direction “away from line 270” indicatesthat the location of interface 348 in memory device 200 may deviate(e.g., due to process variations) from reference location L_(REF) (e.g.,an intended location) in a direction away from line 270. This means thatthe length of portion 343 in the z-dimension (after memory device 200 isformed) would be greater than the intended length of portion 343 ifinterface 348 moves (e.g., shifts) from reference location L_(REF) in adirection way from line 270. The length of portion 343 can be the lengthof a conductive plug (e.g., an n-type material) that forms portion 343.The intended length of portion 343 can be measured from line 270 to thelocation of interface 348 at reference location L_(REF) (e.g., anintended location).

In FIG. 4, the arrow showing a direction “toward line 270” indicatesthat the location of interface 348 in memory device 200 may deviate(e.g., due to process variations) from reference location L_(REF) (e.g.,an intended location) in a direction toward line 270. This means thatthe length of portion 343 in the z-dimension (after memory device 200 isformed) would be less than the intended length of portion 343 ifinterface 348 moves (e.g., shifts) from reference location L_(REF) in adirection toward line 270.

In FIG. 4, curves 401 and 402 represent two example situations showingthe effect of deviation (e.g., due to process variations) in thelocation of interface 348 on the amount of erase GIDL current in memorydevice 200. Curve 401 shows a situation where line 280_1 _(A) andtransistor 286 (FIG. 3) are removed from memory device 200 (e.g., memorydevice 200 without line 280_1 _(A) and transistor 286). Curve 402 showsa situation where line 280_1 _(A) and transistor 286 are included inmemory device 200 as shown in FIG. 2A through FIG. 3.

As shown by curve 401 (without line 280_1 _(A) and transistor 286 inmemory device 200), the amount of erase GIDL current is lower if thelocation of interface 348 varies and moves from reference locationL_(REF) toward line 270 (moves closer to line 270). A lower amount oferase GIDL may degrade the erase operations of memory device 200.

In contrast, as shown by curve 402 (with line 280_1 _(A) and transistor286 in memory device 200), the amount of erase GIDL current can remainrelatively unchanged (e.g., remain stable) if the location of interface348 varies and moves from reference location L_(REF) in a directioneither away from (farther from) line 270 or toward (closer to) line 270.Further, curve 402 also shows a higher amount of erase GIDL current thancurve 401, meaning that that memory device 200 having line 280_1 _(A)and transistor 286 can generate more erase GIDL current than memorydevice 200 without line 280_1 _(A) and transistor 286.

In sum, with the inclusion of line 280_1 _(A) and transistors 286 inmemory device 200, a relatively higher amount of erase current can begenerated in memory device 200 in comparison with a situation where line280_1 _(A) and transistors 286 are not included in memory device 200.Thus, the inclusion of line 280_1 _(A) and transistors 286 in memorydevice 200 can improve the erase operations of memory device 200.Moreover, since the inclusion of line 280_1 _(A) and transistors 286 inmemory device 200 allows the amount of erase GIDL current to remainrelatively unchanged in memory device 200, the operations (e.g., eraseoperations) of memory device 200 can be less susceptible to variationsin the location of interface 348. This can improve the reliability ofmemory device 200.

FIG. 5A shows a block diagram of a portion of a memory device 500, whichcan be a variation of memory device 200 of FIG. 2A, according to someembodiments described herein. Memory device 500 includes elementssimilar to or identical to those of memory device 200. For simplicity,the description of similar or identical elements between memory device500 (FIG. 5A through FIG. 6) and memory device 200 (FIG. 2A through FIG.3) is not repeated.

Differences between memory devices 200 and 500 include differencesbetween transistor gate lines coupled to circuits (e.g., top GIDLcurrent generator circuits) 285_1, 285_2, 285_3, and 285_4 and circuits(e.g., to bottom GIDL current generator circuits) 287_1, 287_2, 287_3,and 287_4 of devices 200 and 500. As shown in FIG. 5A, memory device 500lacks lines (e.g., transistor gate lines) 280_1 _(A), 280_2 _(A), 280_3_(A), and 280_4 _(A) and associated transistors 286. However, memorydevice 500 includes the addition of lines (e.g., transistor gate lines)289_1 _(A) and 289_3 _(A) associated transistors 288.

FIG. 5B shows schematic diagram of memory device 500 of FIG. 5A,according to some embodiments described herein. Memory device 500includes elements similar to or identical to those of memory device 200of FIG. 2B. As shown in FIG. 5B, each of circuits (top GILD currentgenerator circuits) 285_1, 285_2, 285_3, and 285_4 can include one oftransistors 286. For simplicity, fewer than all of circuits 285_1,285_2, 285_3, 285_4 are labeled in FIG. 5B. Each of circuits (bottomGILD current generator circuits) 287_1, 287_2, 287_3, and 287_4 caninclude two of transistors 288. For simplicity, fewer than all ofcircuits 287_1, 287_2, 287_3, and 287_4 are labeled in FIG. 5B. Lines289_1 _(A) and 289_3 _(A) can be coupled to the gates of respectivetransistors among transistors 288.

FIG. 5C shows a schematic diagram of a portion of memory device 500 ofFIG. 5B including line 270, circuits 285_1, 285_2, 285_3, 285_4, selectcircuits 241, 242, 247, and 248, memory cell strings 231, 232, 237, and238, select circuits 241′, 242′, 247′, and 248′, circuits 287_1, 287_2,287_3, and 287_4, and line 299, according to some embodiments describedherein. As shown in FIG. 5C, select gates 263 and 264 of each of selectcircuits 241′, 242′, 247′, and 248′ can be coupled in series with twotransistors among transistors 288 between line 299 and a respectivememory cell string among memory cell strings 231, 232, 237, and 238.

FIG. 5D shows example waveforms of signals BL0, BL1, BL2, GG, SGD_(A),SGD_(B), SGS_(A), SGS_(B), GG′_(A), and GG′_(B), and SRC of memorydevice 500 (FIG. 5A through FIG. 5C) during example erase, write, andread operations, according to some embodiments described herein. FIG. 5Domits other signals of memory device 500 (e.g., signals shown in FIG.5C) to help focus on the embodiments of the memory device describedherein. During erase, write, and read operations, the omitted signalscan be provided with voltages having values known to those skilled inthe art.

The waveforms of FIG. 5D are similar to the waveforms of FIG. 2D exceptfor the omission of signal GG_(A) and for addition of signal GG′_(A). Asshown in FIG. 5D, the waveforms of signal GG′_(A) can be the same as thewaveforms of signal GG_(A) (FIG. 2D). During the erase operation ofmemory device 500, transistors 286 and 288 in respective circuits 285_1,285_2, 285_3, 285_4, 287_1, 287_2, 287_3, and 287_4 can operate togenerate GIDL current to help the erase operation. For example, the GIDLcurrent generated by transistors 286 and 288 during the erase operationmay speed up the charging of the body of the memory cell strings in theselected block in preparation for information in memory cells of thememory cell strings of the selected block to be erased.

FIG. 6 shows a side view of a structure of a portion of memory device500, according to some embodiments described herein. The structure ofmemory device 500 in FIG. 6 corresponds to part of the schematic diagramof memory device 500 shown in FIG. 5C. The portion of memory device 500shown in FIG. 6 includes elements similar to or identical to those ofmemory device 200 of FIG. 3. Differences between memory device 200 (FIG.3) and memory device 500 (FIG. 6) include the omission of line 280_1_(A) and an associated transistor 286 in circuit 285_1 _(A) and theaddition of line 289_1 _(A) and an associated transistor 288 in circuit287_1. As shown in FIG. 6, transistor 288 associated with line (e.g.,transistor gate line) 289_1 _(A) can be located in level 606 along asegment (segment at level 606) of pillar 331. Line 289_1 _(A) can alsobe located in level 606 along a segment (segment at level 606) of pillar331.

As shown in FIG. 6, memory device 500 includes an interface 648 inpillar 331. Interface 648 is the location where portion 346 (e.g., thematerial of portion 346 (e.g., an n-type doped region that forms portion346)) contacts portion 344 (e.g., contacts the material of portion 344).FIG. 6 shows an example where interface 648 is located (e.g.,positioned) at approximately level 606. However, interface 648 can belocated (e.g., positioned) at another location in pillar 331 (e.g., at alocation between levels 307 and 606). As described below with referenceto FIG. 7, the structure of memory device 500 can allow its operations(e.g., erase operation) it to be less susceptible to process variations(process of forming memory device 500). This allows memory device 500 tomaintain its operations even if the location of interface 648 maydeviate from its intended location (e.g., due to process variations).

FIG. 7 is a graph showing an example relationship between the location(e.g., position) of interface 648 and erase GIDL current generatedduring an erase operation of memory device 500 of FIG. 6, according tosome embodiments described herein. The following description refers toFIG. 6 and FIG. 7. In FIG. 7, a reference location L_(REF) can representan intended (e.g., desired) location for interface 648 at which eraseGIDL current is expected (e.g., based on design simulation) to be at anintended amount (e.g., a desired amount) for an erase operation ofmemory device 500. As an example, reference location L_(REF) ofinterface 648 can be the location in pillar 331 at level 606 as shown inFIG. 6.

In FIG. 7, the arrow showing a direction “away from line 299” indicatesthat the location of interface 648 in memory device 500 may deviate(e.g., due to process variations) from reference location L_(REF) (e.g.,an intended location) in a direction away from line 299. This means thatthe length of portion 346 in the z-dimension (after memory device 500 isformed) would be greater than the intended length of portion 346 ifinterface 648 moves (e.g., shifts) from reference location L_(REF) in adirection way from line 299. The length of portion 346 can be the lengthof a diffusion region (e.g., an n-type doped region) that forms portion346. The intended length of portion 346 can be measured from line 299 tothe location of interface 648 at reference location L_(REF) (e.g., anintended location).

In FIG. 7, the arrow showing a direction “toward line 299” indicatesthat the location of interface 648 in memory device 500 may deviate(e.g., due to process variations) from reference location L_(REF) (e.g.,an intended location) in a direction toward line 299. This means thatthe length of portion 346 in the z-dimension (after memory device 200 isformed) would be less than the intended length of portion 346 ifinterface 648 moves (e.g., shifts) from reference location L_(REF) in adirection toward line 299.

In FIG. 7, curves 701 and 702 represent two example situations showingthe effect of deviation (e.g., due to process variations) in thelocation of interface 648 on the amount of erase GIDL current in memorydevice 500. Curve 701 shows a situation where line 289_1 _(A) andtransistor 288 (FIG. 6) are removed from memory device 500 (e.g., memorydevice 500 without line 289_1 _(A) and transistor 288). Curve 702 showsa situation where line 289_1 _(A) and transistor 288 are included inmemory device 500 as shown in FIG. 5A through FIG. 6.

As shown by curve 701 (without line 289_1 _(A) and transistor 288 inmemory device 500), the amount of erase GIDL current is lower if thelocation of interface 648 varies and moves from reference locationL_(REF) toward line 299 (moves closer to line 299). A lower amount oferase GIDL may degrade the erase operations of memory device 500.

In contrast, as shown by curve 702 (with line 289_1 _(A) and transistor288 in memory device 500), the amount of erase GIDL current can remainrelatively unchanged (e.g., remain stable) if the location of interface648 varies and moves from reference location L_(REF) in a directioneither away from (farther from) line 299 or toward (closer to) line 299.

In sum, the inclusion of line 289_1 _(A) and transistor 288 in memorydevice 500 allows the amount of erase GIDL current to remain relativelyunchanged in memory device 500. Thus, the operations (e.g., eraseoperations) of memory device 500 can be less susceptible to variationsin the location of interface 648. This can improve the reliability ofmemory device 500.

FIG. 8A shows a block diagram of a portion of a memory device 800, whichcan be a variation of memory device 200 of FIG. 2A and memory device 500of FIG. 5A, according to some embodiments described herein. Memorydevice 800 includes elements similar to or identical to those of memorydevices 200 and 500. For simplicity, the description of similar oridentical elements between memory devices 800 and memory devices 200 and500 is not repeated.

Memory device 800 can include a combination of memory devices 200 and500. For example, circuits (e.g., top GIDL current generator circuits)285_1, 285_2, 285_3, and 285_4 of memory device 800 can be the same asthose of memory device 200 (FIG. 2A), and circuits (e.g., bottom GIDLcurrent generator circuits) 287_1, 287_2, 287_3, and 287_4 of memorydevice 800 can be the same as those of memory device 500 (FIG. 5A).

FIG. 8B shows a schematic diagram of memory device 800 of FIG. 8A,according to some embodiments described herein. Memory device 800includes elements similar to or identical to those of memory device 200of FIG. 2B and memory device 500 of FIG. 5B. As shown in FIG. 8B, eachof circuits 285_1, 285_2, 285_3, and 285_4 can include two oftransistors 286 (which are the same as those of memory device 200 ofFIG. 2B), and each of circuits 287_1, 287_2, 287_3, and 287_4 caninclude two of transistors 288 (which are the same as those of memorydevice 500 of FIG. 5B).

FIG. 8C shows a schematic diagram of a portion of memory device 800 ofFIG. 8B including line 270, circuits 285_1, 285_2, 285_3, 285_4, selectcircuits 241, 242, 247, and 248, memory cell strings 231, 232, 237, and238, select circuits 241′, 242′, 247′, and 248′, circuits 287_1, 287_2,287_3, and 287_4, and line 299, according to some embodiments describedherein.

FIG. 8D shows example waveforms of signals BL0, BL1, BL2, GG_(A),GG_(B), SGD_(A), SGD_(B), SGS_(A), SGS_(B), GG′_(A), GG′_(B), and SRC ofmemory device 800 (FIG. 8A through FIG. 8C) during example erase, write,and read operations, according to some embodiments described herein.FIG. 8D omits other signals of memory device 800 (e.g., signals shown inFIG. 8C) to help focus on the embodiments of the memory device describedherein. During erase, write, and read operations, the omitted signalscan be provided with voltages having values known to those skilled inthe art. The waveforms of FIG. 8D are the same as the waveforms ofportions of FIG. 2D and FIG. 5D. For example, the waveforms of signalsGG_(A) and GG_(B) in FIG. 8D are the same as the waveforms of signalsGG_(A) and GG_(B) of FIG. 2D. The waveforms of signals GG′_(A) andGG′_(B) in FIG. 8D are the same as the waveforms of signals GG′_(A) andGG′_(B) of FIG. 5D.

FIG. 9 shows a side view of a structure of a portion of memory device800, according to some embodiments described herein. The structure ofmemory device 800 in FIG. 9 corresponds to part of the schematic diagramof memory device 800 shown in FIG. 8C. The portion of memory device 800shown in FIG. 9 includes elements similar to or identical to those ofmemory device 200 of FIG. 3 and memory device 500 of FIG. 6. Forexample, as shown in FIG. 9, lines 280_1 _(A) and 280_1 _(B) andtransistors 286 are the same as lines 280_1 _(A) and 280_1 _(B) andtransistors 286 of FIG. 3, and lines 289_1 _(A) and 289_1 _(B) andtransistors 288 in FIG. 9 are the same as lines 289_1 _(A) and 289_1_(B) and transistors 288 of FIG. 6. Memory device 800 (FIG. 8A throughFIG. 9) can have improvements similar to those of memory devices 200 and500 described above with reference to FIG. 2A though FIG. 7.

FIG. 10, FIG. 11, and FIG. 12 show sequential stages in exampleprocesses of forming a memory device 1000, according to some embodimentsdescribed herein. The processes described with reference to FIG. 10through FIG. 12 can be used to form memory device 200 (FIG. 3), memorydevice 500 (FIG. 6), and memory device 800 (FIG. 9) described above withreference to FIG. 1 through FIG. 9. Some of the processes of formingmemory device 1000 and some of the elements of memory device 1000 may bereadily known to those skilled in the art. Thus, to help focus on theembodiments described herein, some of the processes of forming memorydevice 1000 shown FIG. 10 through FIG. 12 and additional processes tocomplete memory device 1000 are omitted. Further, for simplicity,similar or identical elements among the memory devices in FIG. 2Athrough FIG. 12 are given the same labels.

FIG. 10 shows memory device 1000 after materials 355′ and 1002 areformed over line (e.g., source) 299 and substrate 390. Forming materials355′ and 1002 can include depositing alternating dielectric materials(e.g., alternating layers of materials 355′ and layers of materials1002) over line 299 and substrate 390. Materials 355′ can include anoxide of silicon (e.g., silicon dioxide SiO₂). Materials 1002 caninclude a combination of silicon and nitrogen (e.g., silicon nitriteSiNO₄). Materials 1002 can be formed in each of levels 606 and 307through 317 of memory device 1000 (e.g., each layer of materials 1002can be formed in a respective level among levels 606 and 307 through317).

As shown in FIG. 10, materials 355′ can be formed to have respectivethicknesses that are defined by (e.g., equal to) respective distances(vertical distances) D1, D1′, D1″, D2, D2′, D3, D4, and D4′. DistancesD1, D1′, D1″, D2, D2′, D3, D4, and D4′ are the same as those of FIG. 3,FIG. 6, and FIG. 9. As described above with reference to FIG. 3, FIG. 6,and FIG. 8, distances D1, D1′, D1″, D2, D2′, D3, D4, and D4′ can be thesame (e.g., substantially equal). Thus, in FIG. 10, the thicknesses ofmaterials 355′ can be the same (e.g., substantially equal).

Materials 1002 can be formed to have respective thicknesses T1, T2, T2′,T3, and T3′, which can be same (e.g., substantially equal). ThicknessesT1, T2, T2′, T3, and T3′ are the same as those shown in FIG. 3, FIG. 6,and FIG. 9. In FIG. 10, a location 1031 (between two dashed lines)indicates a location at which portions of materials 335′ and 1002 willbe removed to form a hole in materials 335′ and 1002 (described below).

FIG. 11 shows memory device 1000 after some elements of memory device1000 are formed. Such memory elements include a portion of pillar 331,memory cell string 231, control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀,lines (e.g., transistor gate lines) 280_1 _(A) and 280_1 _(B), selectlines 281 _(A) and 281 _(B), 281′_(A), and 281′_(B), and lines (e.g.,transistor gate lines) 289_1 _(A) and 289_1 _(B), structure 330, andother elements (as shown in FIG. 11) that can be similar to those ofmemory device 200 (FIG. 3), memory device 500 (FIG. 6), and memorydevice 800 (FIG. 9).

Forming the elements of memory device 1000 in FIG. 11 can include usinga process such as a damascene process or other processes. For example,after the materials 355′ and 1002 (FIG. 10) are formed, a hole (avertical opening, not shown in FIG. 11) can be formed in materials 355′and 1002 at location 1031 (FIG. 10). The hole can be formed by removing(e.g., by etching) parts of materials 355′ and 1002 at the location 1031(FIG. 10) and leaving a remaining part of materials 355′ (which are thematerials of dielectrics 355 in FIG. 11 where the hole was not formed)and leaving a remaining part of materials 1002 (not shown in FIG. 11) atrespective levels 606 and 307 through 317. The bottom of the hole can beat line 299 (e.g., at a top surface of line 299). After the hole isformed, as shown in FIG. 11, memory cell string 231 (including structure330) can be formed at the location of the hole. Other structures (e.g.,portions 344, 345, 346, and parts of portions 343 of pillar 331) ofmemory device 1000 can also be formed at the location of the hole.

After the portions of pillar 331 and structure 330 are formed, theremaining part of materials 1002 (where the hole was not formed) can beremoved (e.g., by etching). Removing materials 1002 can include formingslits (e.g., not shown in FIG. 11) in the remaining part of materials355′ and in the remaining part of materials 1002. Such slits (e.g.,vertical openings) can be part of a damascene process used to formmemory device 1000. After the slits are formed, material 1002 can besubsequently etched away through the slits, thereby leaving vacancies(e.g., spaces) at the locations on each of levels 606 and 307 through317 where materials 1002 were (before their removal). Since thethicknesses of materials 1002 (FIG. 10) can be the same (as discussedabove), the spaces where materials 1002 were removed can also have thesame thickness (e.g., same vertical distance).

After the removal of materials 1002, conductive material (e.g., metalsuch as tungsten or other conductive materials) may be formed (e.g.,filled) in the vacancies (e.g., the spaces on each of levels 606 and 307through 317) where materials 1002 were removed. As shown in FIG. 11, theconductive materials on levels 606 and 307 through 317 form therespective lines (e.g., transistor gate lines) 280_1 _(A) and 280_1_(B), select lines 281 _(A) and 281 a, control lines 220 ₀, 221 ₀, 222₀, and 223 ₀, select lines 281′_(A) and 281′, and lines (e.g.,transistor gate lines)²⁸ 9_1 _(A) and 289_1 _(B) of memory device 1000.

Thus, as described above, lines 280_1 _(A) and 280_1 _(B), select lines281 _(A) and 281 _(B), control lines 220 ₀, 221 ₀, 222 ₀, and 223 ₀,select lines 281′_(A) and 281′_(B), and lines 289_1 _(A) and 289_1 _(B)of memory device 1000 can be formed concurrently (formed by the sameprocess step (e.g., the same deposition step)). Further, lines 280_1_(A) and 280_1 _(B), select lines 281 _(A) and 281 _(B), control lines220 ₀, 221 ₀, 222 ₀, and 223 ₀, select lines 281′_(A) and 281′_(B), andlines 289_1 _(A) and 289_1 _(B) can also be formed from the sameconductive material (e.g., metal or other conductive materials).

FIG. 12 shows memory device 1000 after other elements of memory device1000 are formed. Such elements include additional conductive materialsat portions 343 to complete pillar 331, and other portions (e.g., line270) of memory device 1000.

As shown in FIG. 12, memory device 1000 can include elements that aresimilar to or identical to the elements of memory device 800 of FIG. 9.Thus, the processes of forming a memory device 1000 can be used to formmemory device 800 of FIG. 9. One skilled in the art would readilyrecognize that processes similar to the processes of forming a memorydevice 1000 described above with reference to FIG. 10 through FIG. 12can also be used to form memory device 200 (FIG. 6) and memory device800 (FIG. 9).

The illustrations of apparatuses (e.g., memory devices 100, 200, 500,800, and 1000) and methods (e.g., operating methods associated withmemory devices 100, 200, 500, and 800, and methods (e.g., processes) offorming these memory devices) are intended to provide a generalunderstanding of the structure of various embodiments and are notintended to provide a complete description of all the elements andfeatures of apparatuses that might make use of the structures describedherein. An apparatus herein refers to, for example, either a device(e.g., any of memory devices 100, 200, 500, 800, and 1000) or a system(e.g., a computer, a cellular phone, or other electronic system) thatincludes a device such as any of memory devices 100, 200, 500, 800, and1000.

Any of the components described above with reference to FIG. 1 throughFIG. 12 can be implemented in a number of ways, including simulation viasoftware. Thus, apparatuses (e.g., memory devices 100, 200, 500, 800,and 1000 or part of each of these memory devices, including a controlunit in these memory devices, such as control unit 116 (FIG. 1))described above, may all be characterized as “modules” (or “module”)herein. Such modules may include hardware circuitry, single and/ormulti-processor circuits, memory circuits, software program modules andobjects and/or firmware, and combinations thereof, as desired and/or asappropriate for particular implementations of various embodiments. Forexample, such modules may be included in a system operation simulationpackage, such as a software electrical signal simulation package, apower usage and ranges simulation package, a capacitance-inductancesimulation package, a power/heat dissipation simulation package, asignal transmission-reception simulation package, and/or a combinationof software and hardware used to operate or simulate the operation ofvarious potential embodiments.

Memory devices 100, 200, 500, 800, and 1000 may be included inapparatuses (e.g., electronic circuitry) such as high-speed computers,communication and signal processing circuitry, single or multi-processormodules, single or multiple embedded processors, multicore processors,message information switches, and application-specific modules includingmultilayer, multichip modules. Such apparatuses may further be includedas subcomponents within a variety of other apparatuses (e.g., electronicsystems), such as televisions, cellular telephones, personal computers(e.g., laptop computers, desktop computers, handheld computers, tabletcomputers, etc.), workstations, radios, video players, audio players(e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players),vehicles, medical devices (e.g., heart monitor, blood pressure monitor,etc.), set top boxes, and others.

The embodiments described above with reference to FIG. 1 through FIG. 12include apparatuses and methods of using and forming such apparatuses.An apparatus among the apparatuses includes first and second conductivematerials located in respective first and second levels of theapparatus, a pillar including a length extending between the first andsecond conductive materials, memory cells and control lines locatedalong the pillar, a first select gate and a first select line locatedalong the pillar between the first conductive material and the memorycells, a second select gate and a second select line located along thepillar between the first conductive material and the first select line,a first transistor and a first transistor gate line located along thepillar between the first conductive material and the first select line,and a second transistor and a second transistor gate line located alongthe pillar between the first conductive material and the firsttransistor. Other embodiments including additional apparatuses andmethods are described.

The above description and the drawings illustrate some embodiments ofthe invention to enable those skilled in the art to practice theembodiments of the invention. Other embodiments may incorporatestructural, logical, electrical, process, and other changes. Examplesmerely typify possible variations. Portions and features of someembodiments may be included in, or substituted for, those of others.Many other embodiments will be apparent to those of skill in the artupon reading and understanding the above description.

What is claimed is:
 1. An apparatus comprising: a substrate; aconductive material located over the substrate; a pillar contacting theconductive material and having a length extending between the firstconductive material and the substrate; memory cells and control lineslocated along the pillar and between the conductive material and thesubstrate; a first select gate and a first select line located along thepillar and between the conductive material and the memory cells; asecond select gate and a second select line located along the pillar andbetween the first conductive material and the first select line; a firstadditional conductive material located along the pillar and between theconductive material and the second select line; and a second additionalconductive material located along the pillar and between the conductivematerial and the first additional conductive material, wherein thepillar includes a conductive portion and a dielectric portion, theconductive portion contacts the dielectric portion at an interface, andthe interface is located at a level between levels of the first selectline and the second additional conductive material.
 2. The apparatus ofclaim 1, further comprising a data line, wherein the conductive materialis part of the data.
 3. The apparatus of claim 1, wherein the conductiveportion of the pillar includes polycrystalline silicon.
 4. The apparatusof claim 1, wherein the conductive portion of the pillar includes n-typematerial.
 5. The apparatus of claim 1, wherein each of the memory cellsincludes a structure configured to store information, and the structureis polycrystalline silicon structure.
 6. The apparatus of claim 1,wherein each of the memory cells includes a structure configured tostore information and the structure is a dielectric structure.
 7. Theapparatus of claim 1, wherein the memory cells, and the first and secondselect gates have a same structure.
 8. The apparatus of claim 1, whereinthe control lines and the first and d select lines are separated from aconductive channel of the pillar by a same distance.
 9. The apparatus ofclaim 1, wherein the control lines, the first and second select lines,and first and second additional conductive materials include a samematerial.
 10. The apparatus of claim 1, wherein a material of each ofthe control lines is metal.
 11. An apparatus comprising. a substrate; aconductive material located over the substrate; a pillar contacting theconductive material; memory cells and control lines located along thepillar, the conductive material located between the memory cells and thesubstrate; a first select gate and a first select line located along thepillar and between the memory cells and the conductive material; asecond select gate and a second select line located along the pillar andbetween the first select line and the conductive material; a firstadditional conductive material located along the pillar and between thesecond select line and the conductive material; and a second additionalmaterial located along the pillar and between the first additionalconductive material and the conductive material, wherein the pillarincludes a first conductive portion and a second conductive portion, thefirst conductive portion contacts the second conductive portion at aninterface, and the interface is located at a level between levels of thefirst select line and the second additional conductive material.
 12. Theapparatus of claim 11, further comprising a source line, wherein theconductive material is part of the source.
 13. The apparatus of claim11, wherein at least one of the first and second the conductive portionsof the pillar includes polycrystalline silicon.
 14. The apparatus ofclaim 11, wherein each of the memory cells includes a structureconfigured to store information, and the structure is polycrystallinesilicon structure.
 15. The apparatus of claim 11, wherein each of thememory cells includes a structure configured to store information, andthe structure is a dielectric structure.
 16. An apparatus comprising: afirst conductive material located in a first level of the apparatus; asecond conductive material located in a second level of the apparatus; apillar including a length extending between the first and second levelsand contacting the first and second conductive materials; memory cellsand control lines located along the pillar and between the first andsecond conductive materials; a first select gate and a first select linelocated along the pillar between the first conductive material and thememory cells; a second select gate and a second select line locatedalong the pillar and between the first conductive material and the firstselect line: a first additional conductive material located along thepillar and between the first conductive material and the second selectline; a second additional conductive material located along the pillarand between the first conductive material and the first additionalconductive material, wherein the pillar includes a conductive portionand a dielectric portion, the conductive portion contacts the dielectricportion at a first interface, and the first interface is located at alevel between levels of the first select line and the second additionalconductive material; a third select gate and a third select line locatedalong the pillar and between the memory cells and the second conductivematerial; a fourth select gate and a fourth select line located alongthe pillar and between the third line and the second conductivematerial; a third additional conductive material located along thepillar and between the fourth select line and the second conductivematerial; and a fourth additional material located along the pillar andbetween the third additional conductive material and the secondconductive material, wherein the pillar includes a first additionalconductive portion and a second additional conductive portion, the firstadditional conductive portion contacts the second additional conductiveportion at a second interface, and the second interface is located at alevel between levels of the third select line and the fourth additionalconductive material.
 17. The apparatus of claim 16, further comprising adata line and a source, wherein the first conductive material is part ofthe data line, and the second conductive material is part of the source.18. The apparatus of claim 16, wherein the first conductive portion ofthe pillar includes polycrystalline silicon.
 19. The apparatus of claim18, wherein the second conductive portion of the pillar includespolycrystalline silicon.
 20. The apparatus of claim 16, wherein thecontrol lines, the first, second, third, and fourth select lines, andthe first, second, third, and fourth additional conductive materials areseparated from a conductive channel of the pillar by a same distance.